A stable CPU is not a stable computer
An x86 or RISC-V binary may survive the processor generation and still depend on a disappearing OS version, GPU stack, driver model, firmware interface or device implementation.
A stable whole-computer ISA for software that can remain portable, predictable and executable across generations of hardware.
Modern systems preserve a CPU instruction set while leaving the rest of the machine — graphics, storage, audio, networking, peripherals, boot and accelerators — behind unstable interfaces. PMA extends the idea of an ISA outward until software sees a complete, durable computer.
An x86 or RISC-V binary may survive the processor generation and still depend on a disappearing OS version, GPU stack, driver model, firmware interface or device implementation.
Software targets a named PMA profile containing CPU, memory, timers, device discovery and standardized machine devices. Old profiles remain implementable forever.
New silicon may translate old PMA operations internally, just as modern CPUs translate long-lived instruction sets into radically different micro-operations.
An application may run above an OS or directly on the machine. In either case the preserved artifact can be the actual executable environment, not merely source code that must be ported again.
The interface is permanent. The implementation is disposable.
This draft is intended to be small enough to implement, critique and replace.
The full normative spec — every device, table and draft rule — lives in the PDF, not on this page.
A program rarely targets a computer. It targets a transient combination of CPU ISA, operating system ABI, graphics API, driver stack, firmware behavior, device protocols and vendor tooling.
The goal is not fewer transistors. It is fewer moving contracts above the transistors.
The same functionality is repeatedly re-expressed for new platform APIs and device stacks.
High-performance and real-time software depends on layers it does not control.
Old source may survive while the exact executable environment becomes difficult or impossible to reproduce.
PMA treats the machine interface itself as a long-lived public artifact.
The OS owns protection, processes, filesystems, networking policy and resource sharing. An old OS image can itself be the preserved binary environment.
A game, instrument, control system or high-assurance appliance can own the machine directly and bundle only the functionality it needs.
Profiles are the unit of portability: software may assume every mandatory feature of the profile exists.
The device model is the heart of PMA. Every device — storage, network, audio, graphics, tensor, peripheral I/O — is a simple asynchronous machine: shared-memory command queues, completion queues, memory-mapped control blocks and interrupts.
One transport shape, different payloads.
PMA_DeviceHeader
magic u32
class_id u32
interface_version u32
feature_bits u64
queue_count u16
event_count u16
queue_table_ptr u64
class_mmio_ptr u64
Intentionally similar in spirit to proven interfaces such as VirtIO — PMA applies the same shape to the physical machine, not just virtual hardware.
The first public artifact is a single PMA boot image that exercises the complete minimal computer — no Linux, no Windows, no vendor driver.
The exact same boot image runs unchanged in:
No source rebuild is required to move between implementations of the same profile.
Do not begin with a high-end SoC. Begin by making the architecture undeniable.
PMA is deliberately incomplete. These are the places where confidence would be premature.
Exactly which RISC-V profile and vector features become permanent in PMA-Computer-1? How should future CPU profiles coexist without fragmenting the software base?
What is the lowest stable abstraction that can be implemented efficiently by future GPUs without exposing ephemeral wave, tile or cache details?
Which coherence guarantees are mandatory between CPU, GPU, NPU and DMA devices? Where are explicit flush/invalidate operations required?
Which floating-point and transcendental behaviors are bit-exact, and which are bounded but implementation-dependent?
Should older accelerator ISAs be supported by hardware translation, firmware translation, or a protected compatibility engine?
Who is allowed to ratify a permanent feature? What proof — emulator, formal model, FPGA, independent implementation — is required before a 1.0 promise is made?
The architecture should be easy to extend and deliberately hard to ratify.
RISC-V's RVA23 profiles solve the CPU. RISC-V IOMMU solves device isolation. OASIS VirtIO proved the device-queue shape works. Arm SystemReady proved there's real demand for standardizing more than the instruction set. PMA takes that same instinct further, and makes it permanent.
RISC-V can provide the permanent CPU. PMA's job is to make the rest of the computer equally boring.
This is v0.1 — an exploratory proposal, concrete enough to implement, benchmark, criticize and replace before any permanence promise is made.